In order to achieve high densification and high performance of a semiconductor package, implementation for mix-loading chips having different performance into one package is proposed. In this case, high-density interconnection between chips, excellent in cost performance, is important (for example, refer to Patent Literature 1).
In Non Patent Literature 1 and Non Patent Literature 2, an aspect of a package-on-package (PoP) for connecting through stacking another different package on a package by flip-chip mounting is described. The PoP is an aspect widely employed in smartphones, tablet terminals and the like.
As other forms for high-density implementation of a plurality of chips, packaging using an organic substrate having a high-density wiring, Fan Out-Wafer Level Package (FO-WLP) having a Through Mold Via (TMV), packaging using a silicon or glass interposer, packaging using a Through Silicon Via (TSV), packaging using a chip embedded in a substrate for transmission between chips, and the like have been proposed.
In particular, as for a semiconductor wiring layer and FO-WLP, when semiconductor chips are mounted, a fine wiring layer for achieving high-density conduction between the semiconductor chips are required (for example, refer to Patent Literature 2).